A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches
Hyunhee Kim, Sungjun Youn, Jihong Kim · 2008
Power dissipation becomes an important issue in modern microprocessors such as chip multiprocessors (CMPs). Especially as the process technology advances below 90nm, the leakage power consumption becomes dominant in the total power dissipation, thus reducing the leakage power consumption is an important design goal for low-power CMPs. In particular, since most CMPs employ a large L2 cache, reducing the leakage power consumption of the L2 cache is critical in realizing low-power CMPs.