Trainable and Low-Cost SMO Pattern Classifier Implemented via MCMC and SFBS Technologies
Chih‐Hsiang Peng, Ta-Wen Kuan, Po‐Chuan Lin, Jhing-Fa Wang, Guo-Ji Wu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2014
This paper presents a multicore and multichannel (MCMC) technology and a synchronous and forward-backward scheduling (SFBS) for the cost reduction of sequential minimal optimization trainable pattern classifier. The MCMC technology uses multiple processing cores that are self-reconfigurable and preconfigurable. For different functions, five self-configurable modes and four preconfigurable modes can be combined to achieve high flexibility. A multichannel hierarchical architecture enables different transfer rates. To minimize communication cost, the SFBS uses synchronous and forward-backward counting for data scheduling. For implementation in reconfigurable FPGAs, MCMC and SFBS are combined for use in synthesis, placement, and routing. Compared with the baseline design, the emulation results show that the proposed architecture has a low area and low power costs (5755 logic elements and 195 mW), respectively. The experimental results confirm the cost improvement achieved by the proposed architecture and methods.