Test clock domain optimization for peak power supply noise reduction during scan
Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James C. M. Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li · 2011
This paper presents a design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting. The proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock. The experimental data on large benchmark circuits show that IR drop are reduced by 38.7% on the average compared with the circuit before optimization. Our proposed technique quickly optimizes a half million gate design within 14 minutes while the commercial IR drop simulation tool took over 3 hours.