Systolic Computational-Memory Architecture for an FPGA-based Flow Solver
Kentaro Sano, Takanori Iizuka, Satoru Yamamoto · Conference proceedings · 2006
This paper presents an FPGA-based flow solver based on the systolic computational-memory architecture. We show that the flow solver based on the fractional-step method with difference schemes can be expressed as a systolic algorithm, and the systolic computational-memory architecture is suitable to design the special-purpose processor for the flow solver. Based on this architecture, we propose a special-purpose processor comprised of a 2D array of cells connected by a 2D mesh network. Each cell has a computational data-path and a local memory. While the whole array stores data as a memory, it also performs highly parallel and scalable floating-point computations with the sufficient memory bandwidth. We report the initial design of the processor for two ALTERA Stratix II FPGAs, and discuss its estimated peak performance that could reach 30 GFLOPS at only 60MHz.