Directory based cache coherence modeller in multiprocessors: Medium insight
Harsh Arora, Rijubrata Mukherjee, Abhijit Bej, Hillol Adak · 2014
In a multiprocessor scenario, cache coherency problem is arisen when there is no data consistency between the private caches and the main memory. The key design aspect for efficient multiprocessor systems is a scalable cache coherence protocol. Directory based approach is used for large scale distributed networks and is seen as a scalable substitute to CMP design, but with the increase in the number of the on-chip cores, the directory based protocol is not scalable beyond a specified number of cores. We inspect several conventional and NUCA based directory protocols like Sparse, Duplicate tag-based and Full map directory protocol and analyze some novel cache coherence protocols intended for multi-core processors. Finally, we suggest a design prototype for a scalable directory based coherence protocol for optimal performance.