A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS
Yatin Hoskote, B.A. Bloechel, G. E. Dermer, Vasantha Erraguntla, David Finan, Jason Howard, D. Klowden, S. Narendra, Greg Ruhl, James W. Tschanz, Sriram R. Vangal, V. Veeramachaneni, H. Wilson, Jianzhong Xu, Nitin Borkar · IEEE Journal of Solid-State Circuits · 2003
This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm2experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W.