Generating instruction sets and microarchitectures from applications
Ing-Jer Huang, Alvin M. Despain · 1994
Abstract—The design of application-specific instruction set pro-cessor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design, and instruction set mapping for the application. We present a method that unifies these three design problems with a single formulation: a modified scheduling/allocation problem with an integrated instruction for-mation process. Micro-operations (MOPs) representing the appli-cation are scheduled into time steps. Instructions are formed and hardware resources are allocated during the scheduling process. The assembly code for the given application is obtained automat-ically at the end of the scheduling process. This approach consid-ers MOP parallelism, instruction field encoding, delay load/store/ branch, conditional execution of MOPs and the retargetability to various architecture templates. Experiments are presented to show the power and limitation of our approach. Performance improvement over our previous work [4] is significant. 1.