An SoC architecture and its design methodology using unifunctional heterogeneous processor array
Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera · 2004
We propose a heterogeneous processor architecture and its design methodology to shorten the design period of the SoC. It enables fast implementation of a system LSI including an embedded CPU and peripheral functional blocks. Each functional block of the sys-tem under design is implemented to a customized processor, in-stead of a peripheral hardwired logic. We customize processors by deleting unneccesarry functionalities, without adding new fea-tures. This eables rapid and bug-free design. Although area, power and performance of the proposed architecture are a little bit inferior to those of hardwired logics, the design period of the processor is considerably minimized, since the ROM pattern (software) and the layout pattern (customized processor, i.e. hardware) can be inde-pendently designed in parallel. 1.