MAINTAINING DIGITAL CLOCKS IN STEP
Anish Arora, Shlomi Dolev, Mohamed G. Gouda · Parallel Processing Letters · 1991
A system of simultaneously triggered clocks is designed to be stabilizing: if the clock values ever differ, the system is guaranteed to converge to a state where all clock values are identical, and are subsequently maintained to be identical. For an N-clock system, the design uses N registers of 2 log N bits each and guarantees convergence to identical values within N2 "triggers".