Model and physical implementation of multi-port PUF in 65 nm CMOS
Yuejun Zhang, Pengjun Wang, Yi Li, Xingxing Zhang, Zhiyi Yu, Yibo Edward Fan · International Journal of Electronics · 2012
In modern cryptographic systems, multi-port physically unclonable function (MPUF) is an efficient mechanism for many security applications, which extracts secret information inherently embedded in the unclonable physical variations and generates multiple secret keys. In this article, we propose an explicit analytic MPUF model, which is useful in predicting the effect of parameter changes on the state as well as in optimizing the design of PUF. Then, a novel MPUF based on register file is designed and fabricated in TSMC low-power 65 nm CMOS technology. There are four ports in the MPUF, and each port produces a 256-bit key. The chip has an area of 0.045 mm2, and has a peak clock frequency of 1.25 GHz at 1.2 V. The average power consumption is 13.8 mW at 27°C. Being multi-ports technology and high operation frequency, the throughput of MPUF improves about 50 times compared to the other works. We carry out a robust test by varying the operational conditions such as supply voltage, temperature and noise. The measured results show that the reliability achieves 98.1% at worse case and has a certain improvement compared with the proposed works. The reliability operates at an acceptable range in integrated circuit identification (ICID).