Scalable and fault tolerant restricted shared memory architecture
Gul N. Khan, K. Mahmud · Electronics Letters · 1993
A scalable and fault tolerant restricted shared memory architecture is described which uses dual-port memory blocks for interprocessor communication. For an n processor system, n(n − 1)/2 dual-port memory blocks are organised in the form of a triangular matrix. Multiple processors can communicate concurrently as unique and dedicated dual-port memory blocks connect different pairs of processors.