Multiple clock domain synchronization for network on chip architectures
Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande · 2007
The Network-on-Chip (NoC) is emerging as a revolutionary methodology in solving the performance limitations arising out of long interconnects. Continued advancement of NoC designs is heavily dependent on the ability to effectively communicate among the constituent Intellectual Property (IP) blocks/Embedded cores, as well as manage/reduce energy dissipation. This paper presents a low-latency, low-energy synchronization mechanism for Network on Chip architectures, which enables the network to span a system-on-chip (SoC) with multiple independent clock domains. The proposed interface scheme has been compared to another existing scheme and shown to outperform it in terms of latency and energy dissipation.