Opposite-phase register switching for peak current minimization
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh · ACM Transactions on Design Automation of Electronic Systems · 2009
In a synchronous sequential circuit, huge current peaks are often observed at the moment of clock transition (since all registers are clocked). Previous works focus on reducing the number of switching registers. However, even though the switching registers are the same, different combinations of switching directions still result in different peak currents. Based on that observation, in this article, we propose an ECO (engineering change order) approach to minimize the peak current by considering the switching directions of registers. Our approach is well suitable for reducing the peak current in IC testing. Experimental data consistently show that our approach works well in practice.