A 146- $hbox mm^2$ 8-Gb Multi-Level NAND Flash Memory With 70-nm CMOS Technology
Takahiko Hara, Koichi Fukuda, K. Kanazawa, Noboru Shibata, Koji Hosono, H. Maejima, M. Nakagawa, T. Abe, M. Kojima, M. Fujiu, Yoshinori Takeuchi, K. Amemiya, Midori Morooka, Tatsuya Kamei, Hiroaki Nasu, C.-M. Wang, K. Sakurai, Naoya Tokiwa, H. Waki, Tooru Maruyama · IEEE Journal of Solid-State Circuits · 2005
An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.