The design and implementation of a VLSI chess move generator
Carl W. Ebeling, Andrew J. Palay · ACM SIGARCH Computer Architecture News · 1984
Communication is a basic problem when using VLSI technology to implement large parallel circuits. Valuable chip area must be used to run wires connecting components on a chip and current packaging technology restricts the amount of communication that can cross chip boundaries. This paper presents a large parallel architecture for generating moves in chess and shows how it can be restructured to reduce communication and permit a straightforward VLSI implementation without any performance loss. The result is a move generator comprising 64 identical custom chips performing at a rate of 500,000 moves per second, performance that is comparable to the best existing move generator. The success of the architecture of a component module like a chess move generator depends not only on its performance but on how well it meshes with the rest of the system. We discuss the requirements of a chess move generator in the context of a chess-playing system and describe how each of these are met by our design. Details of the chip design are presented along with a description of how the move generator is built using identical chips.