A Lazy-Updating Snoop Cache Protocol for Transactional Memory
Sekai Ichii, Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama · 2014
In this paper, we propose a new Hardware Transactional Memory (HTM) system for a shared-memory multiprocessor in which elementary processors are connected by a single common bus. One of the key features of our system is a modified snoop cache protocol to reduce overheads on the transactional memory consistency control. By publishing all of modified data in a transaction at once when the transaction commits, our system avoids the overhead on the commit, which would arise from a sequential publication (or write-back to main memory) of each data item in the transaction otherwise. Another feature is a virtualization of a cache layer in the memory hierarchy. When a cache must replace a line which contains speculatively modified data, our system dynamically reallocates the address of the line to another location in main memory, and back up the evicted data to a lower layer cache or main memory. The backed-up data is still under the control of the transactional memory consistency through our snoop cache protocol. By enlarging a cache capacity virtually in this manner, our system can support unbounded transactions which are not limited by the hardware resources in the size and the duration.