Low-power implementation of H.263 codec core dedicated to mobile computing
Morgan Hirosuke Miki, Gen Fujita, Takao Onoye, Isao Shirakawa · Electronics and Communications in Japan (Part III Fundamental Electronic Science) · 2000
This paper describes the VLSI design of the H.263 codec core for low-bit-rate image coding algorithm. In the present core specifically designed for use at mobile terminals, each processing process can be realized by a specific ASIC architecture. Each operation circuit makes use of the coding option to accomplish a high coding efficiency and is realized with a new architecture that seeks as much as possible a small area and a low operating frequency. When the present core is VLSI designed with the top-down ASIC design system COMPASS Design Tools ver. 9, the power consumption at 15-MHz operation is 84.18 mW (with a supply voltage of 3.3 V) with 4.94 mm2 by 0.35-μm CMOS four-layer metal technology. © 2000 Scripta Technica, Electron Comm Jpn Pt 3, 83(11): 74–84, 2000