4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words
K. Johguchi, H. J. Mattausch, T. KOIDE, T. HIRONAKA · IEICE Transactions on Electronics · 2007
The presented unified data/instruction cache design uses multiple banks and features 4 ports, distributed crossbar, different word-length for data and instruction ports, interleaved cache-line words and synchronous access with hidden precharge. A 20.5 KByte storage capacity is integrated in 5-metal-layer CMOS logic technology with 200 nm minimum gate length and a 3.4ns access-cycle time is achieved. The access bandwidth corresponds to 10 ports with standard word-length, while the cost in increased Si-area is only 25% in comparison to a 1-port cache.