FPGA based fast synchronous serial multi-wire links synchronization
Krzysztof T. Pozniak · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2013
The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.