Enhanced Secure Architecture for Joint Action Test Group Systems
Luke Pierce, Spyros Tragoudas · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2012
The implementation of debugging tools through joint action test group (JTAG) has led to increased exposure of intellectual property through the interface. In this brief, the first hardware implementation of a flexible multilevel access security system for the JTAG interface is detailed. The proposed method is user-privilege aware, which allows for higher granularity for controlling user access of individual scan chains. The loading of individual JTAG instructions into scan chains can be blocked based on the credentials of the user. The hardware modifications proposed are compliant with IEEE 1149.1, have minimal timing overhead, and require no modifications to the core logic of the integrated circuit.