Analysis and modelling of parasitic substrate coupling in CMOS circuits
X. Aragonés, Francesc Moll, Miquel Roca, Antonio Rubio · IEE Proceedings - Circuits Devices and Systems · 1995
Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed.