Side-channel leakage on silicon substrate of CMOS cryptographic chip
Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu Ich Hayashi, Naofumi Homma, Shivam Bhasin, Jean‐Luc Danger · 2014
Power supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths. The voltage bounce due to the substrate currents is seen wherever p+ substrate taps on a p-type die and regarded as a substrate noise. An on-chip waveform monitor confirms the side-channel leakage on the silicon substrate from an AES cryptographic module in a 65 nm CMOS demonstrator chip for the first time. The silicon substrate is essentially common to every circuit and inevitably carries the leakage to the observation taps located at the front as well as at the bottom surface of a die, even if the power and ground wires of an AES module are intentionally separated from the other building blocks. Substrate leakage channels may break the hiding of a cryptographic module regarding its location on a die. The physical properties including the distance dependency are experimentally explored.