A Condensed Graph Microprocessor to Drive Parallel Computing.
Padraig J. O'Dowd, Philip D. Healy, John P. Morrison · Parallel and Distributed Processing Techniques and Applications · 2005
This paper discusses the implementation of a Condensed Graph (CG) Microprocessor on a Xilinx FPGA. The initial goal of the Microprocessor is to be the front-end scheduler of a meta-computer, executing applications according to the Condensed Graph Model. The second goal being the realization of a fully fledged parallel machine architecture based on the CG model. The Condensed Graph Model of Computing is a directed graph-based model that is implicitly parallel, easily exposing parallelism in applications expressed as Condensed Graphs. It has been the focus of much research in recent years and has been the centre of many parallel-computing research projects to date. The CG Microprocessor is the first hardware implementation of the CG Model, whose aim is to apply hardware acceleration to the scheduling of computations in a meta-computing environment. Some of the possible future applications that could benefit from the use of the CG Microprocessor are also discussed.