A Low-Cost 256-Point FFT Processor for Portable Speech and Audio Applications
Chao Wang, Woon‐Seng Gan, Ching Chuen Jong, Jianwen Luo · 2007 International Symposium on Integrated Circuits · 2007
In this paper, a low-cost 256-point FFT processor design is presented for portable speech and audio applications. After an intensive review of existing FFT architectures, a single-butterfly FFT architecture is chosen to obtain low cost. In this single-butterfly FFT architecture, a two-multiplier and three-adder pipelined butterfly unit is proposed to calculate the butterflies at different levels, recursively. Compared with other butterfly units, this two-multiplier and three-adder structure obtains the best tradeoff between hardware cost and processing throughput. The supply voltage scaling technique is employed in the FFT processor to achieve substantial power saving. Circuit simulation and implementation results show that the proposed 256-point FFT processor is well suited for portable speech and audio applications.