Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression
Roberto Airoldi, Piia Saastamoinen, Jari Nurmi · 2012
This paper presents the evaluation of a homogeneous Multi-Processor (MP) architecture equipped with a code compression system. The MP architecture is composed by a 3×3 mesh of processing elements interconnected via a hierarchical Network-on-Chip. Each processing element hosts a RISC processor, data and instruction memories, a network interface and an independent code compression system. The so composed system was evaluated in performance, power consumption, logic utilization and obtained compression ratio, while executing significant kernels of wireless communication systems. Results show that the introduction of the code compression system improves the computational density of the architecture (e.g. GOPS/mm2) due to a higher logic-to-memory ratio, while approximately retaining other performance figures in a worst-case analysis.