Architectures for exponentiation in GF(2/sup m/)
P. Andrew Scott, S.J. Simmons, Stafford E. Tavares, L. Peppard · IEEE Journal on Selected Areas in Communications · 1988
Several VLSI architectures for performing exponentiation in GF(2/sup m/) are presented. Two approaches to the architecture design are taken. In the first, all intermediate products of the exponentiation are computed in a sequential fashion to minimize the silicon area. In the second approach, all values of raised to the 2/sup ei/ power, O>