IPNoSys II
Thiago R. B. S. Soares, Ivan Saraiva Silva, Silvio Roberto Fernandes · 2015
The quest for more performance frequently finds some interesting answers in unconventional computing. IPNoSys is a parallel processing platform for packet-based applications. Its hardware architecture is based on network-on-chip (NoC) structure and its applications are executed while the packets are routed through the NoC. This paper presents a new architecture to IPNoSys programming model. IPNoSys II was developed to provide more performance than the original implementation, supporting the same programming model and allowing parallel execution of a larger number of tasks. IPNoSys II was developed in VHDL and prototyped in FPGA board. Experimental results show that the new architecture can reaches performance five times higher than the original one and 19 times faster than a NoC-based MPSoC using SPARC V8 as processors.