A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder
Weiping Wang, Deng Bi, Xin Du, Lijun Ma · IEICE Transactions on Information and Systems · 2007
A novel high-speed and area-efficient Reed-Solomon decoder is proposed, which employs pipelining architecture of minimized modified Euclid (ME) algorithm. The logic synthesis and simulation results of its VLSI implementation show that it not only can operate at a higher clock frequency, but also consumes fewer hardware resources.