A demonstration of co-design and co-verification in a synchronous language
Satnam Singh · 2004
This interactive demonstration illustrates how the synchronous programming language Esterel [3] can be used to design and verify both hardware and software. The interactive demonstration will use a laptop which will be used to drive an Esterel system description all the way to hardware and software which will be implemented on an FPGA using vendor tools. This laptop will also be used to interactively prove challenging properties of the generated system. Additionally an FPGA-based board will be used to execute the generated hardware and software. Esterel has demonstrated very good results for the design of control based systems in either hardware or software. Esterel also has interesting static analysis capabilities for control based systems. This interactive demonstration illustrates that power of combining these two complimentary