Architecture and some properties of digital circuits with boundary scan
Jerzy Kern · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1992
The paper presents basic properties of digital circuits, with a boundary scan testing (BST) subsystem in the circuit architecture. The paper describes the operation and states for test access port controller (TAPC) built in the subsystem. A self-test procedure is presented, based on pseudo-random test generation and signature analysis, done by linear feedback shift registers (LFSR), configured with boundary scan register cells. Characteristics of the pseudo- random signal generator were obtained by simulation method.