Application‐oriented cache memory configuration for energy efficiency in multi‐cores
Bruno de Abreu Silva, Lucas Albers Cuminato, Alexandre C. B. Delbem, Pedro C. Diniz, Vanderlei Bonato · IET Computers & Digital Techniques · 2014
This study describes and evaluates an automated technique that exploits the potential of heterogeneous multi‐core processor (HMP) systems when customised with respect to the number of cores and L1 cache memory sizes using a field programmable gate array fitted with LEON3 cores at its base. The authors evaluated the real energy consumption of the HMP system tuned for a set of 50 application codes using a data‐mining tool for finding code similarities and selecting HMP configurations. The selected HMP system configuration requires a small cache configuration and consumes less energy when compared to a homogeneous system with the same number of cores and only with a very modest increase in execution time.