A reconfigurable pipelined transmultiplexer architecture
P. J. Fernandes, M.M. Jamali, Subhash C. Kwatra, James M. Budinger · 1991
A reconfigurable transmultiplexer that is capable of on-board demultiplexing of a varying number of single channel per carrier frequency division multiple access (FDMA) channels with varying bit rates is presented. The multiplexing algorithm selected for demultiplexing the FDMA channels is the polyphase FFT (fast Fourier transform) method, which requires a bank of filters followed by an FFT operation. A reconfigurable shared filter bank and reconfigurable pipelined FFT architecture are designed to implement the bank of filters and FFT operations for two different cases. The architecture is suitable for satellite on-board processing as it is reconfigurable and modular and can perform its processing in real time without large buffers. The architecture is illustrated specifically for demultiplexing 800 channels, at 64 kbps or a mix of 400 channels at 64 kbps and 12 channels at 2.048 Mbps or 24 channels at 2.048 Mbps.>