A-Port Networks
Michael Pellauer, Muralidaran Vijayaraghavan, Michael W Adler, Arvind Arvind, Joel Emer · ACM Transactions on Reconfigurable Technology and Systems · 2009
Computer architects need to run cycle-accurate performance models of processors orders of magnitude faster. We discuss why the speedup on traditional multicores is limited, and why FPGAs represent a good vehicle to achieve a dramatic performance improvement over software models. This article introduces A-Port Networks, a simulation scheme designed to expose the fine-grained parallelism inherent in performance models and efficiently exploit them using FPGAs.