Programmable logic array optimization techniques
H. F. LI · International Journal of Electronics · 1980
The programmable logic array (PLA) has become a convenient logic element in digital system design. This paper attempts to solve three problems : (i) minimization of the number of input variables (pins) of the functions, (ii) minimization of the number of product. terms (AND-gates) needed, and (iii) the sufficient conditions under which a variable can lie eliminated without, increasing the number of product terms needed by a function. A branch-and-bound algorithm and a ‘ greedy ’ heuristic are developed for the minimization problems.