New Circular-Carry-Select (CCS) architecture for diminished-one modulo 2n+1 addition
Su-Hon Lin, Ming‐Hwa Sheu, Zemin Chen · 2007
The diminished-one modulo 2n+1 addition is an important arithmetic operation for a high-performance residue number system (RNS). In this paper, we propose a new Circular-Carry-Select (CCS) architecture for diminished-one modulo 2n+1 adder. The resulting modulo 2n+1 adder is mainly based on CCS addition block which is simple and regular for all n values. For actual VLSI implementation based on UMC 180nm CMOS technology, the CCS-based diminished-one modulo 2n+1 adder demonstrates the superiority in AreaxTime (AT) performance over those of the famous existing solutions. The area and clock rate for CCS-based modulo 216+1 adder chip are 26746um2and 476MHz respectively.