VLSI design of Reed-Solomon decoder based on new architecture of modified Euclidean algorithm
Xiaoyang Zeng, Zhenyu Gu, Chao Chen, Qianling Zhang · 2003
A RS(255, 223) decoder based on modified Euclidean (mE) algorithm is implemented. A new VLSI architecture of the error-locator and error-evaluator module for mE algorithm is studied. The new architecture can reduce the complexity of the module and the error-probability of the decoder is cut-down also. The RS decoder is implemented using 0.35 mm CMOS technology, and the chip-area is about 30,000 gates, system clock is 65MHz, throughout is about 500Mbits/s. The decoder has the merits of low latency, low complexity and moderate throughput of data.