High-speed hardware architecture for high-definition videotex system
Mitsuru Maruyama · Journal of Electronic Imaging · 1992
A high-speed hardware architecture for an experimental high-definition videotex system for a broadband integrated services digital network is introduced. The key technologies required are high-speed protocol processing, high-speed data transfer, and highspeed picture readout from disks. High-speed protocol processing using a newly developed virtual memory copy, content rearrangement memory, two-bus architecture, and simultaneous editing and analyzing allows a requested 6-MB picture to be displayed within 3s.