Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis
Soumitra Bose, Vishwani D. Agrawal · 2007
Stuck fault coverage estimation for sequential circuits relies on a time expansion model, where combinational techniques are employed for each time-frame. Faults that are hard to detect and require a particular sequence of states are often incorrectly estimated to be detected. This problem is more evident for designs that exhibit low coverage either due to low testability or insufficient vectors that fail to exercise the required sequence of states. This paper illustrates how a simple state traversal analysis can mitigate this problem. For circuits with large number of sequential elements, we propose an entropy based technique that collapses the state graph to be analyzed. Experimental results for larger ISCAS benchmarks show that this technique reduces the coverage estimation error by as much as 50%.