Design and Analysis of Location Caches in a NoC-Based Chip Multiprocessor System
D. Ramakrishnan, Yen-Kuan Wu, Wen B. Jone · Journal of Low Power Electronics · 2010
This research is focused on designing location caches for a NoC-based NUCA (non-uniform cache architecture) system with multiple cores, in combination with a low-leakage L2 cache based on the gated-ground technique. This system architecture helps reduce the power consumption of the L2 cache along with the performance benefit of the on-chip network. The features of CACTI and GEMS are extended to support complete power and performance simulation of the system. The full-system simulation is performed on scientific and multimedia workloads to characterize the NoC-based system. Analysis of the power and performance of the proposed CMP cache system is presented in comparison with the traditional cache structure in different configurations. Simulation results show that the NoC-based system with location caches significantly saves the energy of the cache system over the traditional bus-based system in any configuration and also the NoC-based system without location caches. The system also provides better performance compared to a bus-based system, emphasizing the need to shift to a network-based cache interconnect design which can scale to a large number of cores.