Design and implementation of transaction level processor based on UVM
Yingke Gao, Diancheng Wu, Li Quanquan, Tiejun Zhang, Chaohuan Hou · 2013
As the complexity of integrated circuit increases, the transaction level model (TLM) bridges the architecture and the hardware implementation. With SuperV_EF01 DSP as the research prototype, this paper presents a new method to design and implement the transaction level model based on UVM, which provides plenty of SystemVerilog libraries. This model can accelerate software development and be used as a golden reference model in the verification of RTL model without complex interface function.