A study on shared buffer‐type atm switch
Haruo Kitamura · Electronics and Communications in Japan (Part I Communications) · 1990
Abstract The conventinal shared buffer‐type switch in ATM multiplexes the cells, and a large number of cells is stored in a memory. This produces a problem in that the speed within the switch must be increased, which is limited by the speed of the circuit. This paper proposes a shared buffer‐type switch in which a number of memories are provided, each storing a cell, and the switching is executed without the cell multiplexing. Several features are realized as follows. The required number of buffers is less than in the output buffer type. The priority control and the broadcasting can be realized. There is a flexibility in that the number of input and output lines are arbitrary. If the proposed switch with a high speed is used in the multistage switching network, a switch with an excellent performance such as low‐loss rate and high throughput can be obtained.