System-Level Retiming and Pipelining
Girish Venkataramani, Yongfeng Gu · 2014
In this paper, we examine retiming and pipelining in the context of system-level optimization techniques. Our main contributions are: (a) functionally equivalent retiming and delay balancing as necessary techniques for pipelining and retiming system-level graphs while maintaining numerical fidelity, and (b) clock-rate pipelining, as a new technique that leverages the knowledge of multi-rate design spec to pipeline multi-cycle paths. All these techniques have been implemented within HDL Coder™, a tool that generates synthesizable HDL code from Simulink ® and MATLAB®.