Microprocessor architecture utilizing redundant-binary operation
Takahiro Irita, Takayuki Ogura, Minoru Fujishima, Koichiro Hoh · Systems and Computers in Japan · 1999
In conventional microprocessors, add/subtract instructions require longer execution times than logic/shift operations, caused by carry propagation delay. Therefore, the cycle time is not fully utilized in the execution of such instructions. In this article, an ALU architecture utilizing the redundant binary operations is proposed. Such an architecture admits redundant binary code outputs, and all ALU operations including add/subtract are executed in a short time regardless of the bit width, so that it becomes possible to shorten the stage time of the microprocessor. Further, the specific features of a designed microprocessor using this ALU architecture are investigated. In this microprocessor, fetch and decode instructions and register write-back are carried out as two parallel instructions in two-way superscalars. On the other hand, execution of instructions is carried out one by one in double-clock-speed pipelines. Using this architecture, it becomes possible to execute two simultaneously decoded instructions even if they are dependent on each other. ©1999 Scripta Technica, Syst Comp Jpn, 30(13): 106–115, 1999