Programmable CRC circuit architecture
Ciaran Toal, Sakir Sezer, Xin Yang, Kieran McLaughlin, Dwayne C. Burns, Tiberiu Seceleanu · 2007
This paper presents the design and implementation of a fully programmable Cyclic Redundancy Check (CRC) computation circuit for System on a Chip (SoC) network processing applications. The presented architecture provides flexibly whilst maintaining gigabit throughput rates for frame/packet processing using standard cell technology.