The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3
R. Hori, T. Ueoka, Taku Otani, M. Yoshikawa, Takeshi Fujino · 2013
The exponential increase of photo-mask cost is a serious problem in the SoC fabrication. We have developed the Structured ASIC architecture named VPEX3, which can program logic functions using only three via layers. In the VPEX3 architecture, the logic element (LE) composed of EXOR and NOT gate can realize 22 logic functions. This architecture is effective to reduce the NRE cost for low-volume ASICs, because an intended logic function can be implemented rapidly by only changing three masks. A dedicated CAD system for VPEX3 architecture had been developed in our laboratory, and combinational circuits had been successfully operated on the test chip. In this paper, we propose the novel clock network architecture for implementing sequential logic circuit. Furthermore, we demonstrate the chip design of DES cryptographic circuit using this clock network and our inhouse dedicated CAD system.