Power analysis and implementation of a low-power 300-MHz 8-b×8-b pipelined multiplier
Jinn‐Shyan Wang, Po-Hui Yang · 2002
This paper analyzes the power consumption of an array pipelined multiplier. To precisely realize a low power pipelined multiplier, the analytical model for a clocking system is presented. Simulation results show that the storage element is the key-component in a high performance pipelined multiplier macro. Compared with the conventional DFF and latch, the new low power DFF as PTTFF achieves a total power reduction ranging between 34 and 62 percent in a pipelined multiplier macro.