Accelerating PQMRCGSTAB Algorithm on Xeon Phi
Cheng Chen, Can Qun Yang, Wen Yao, Jin Qi, Qiang Wu · Advanced materials research · 2013
Utilizing iterative method to solve the large sparse linear systems is the key to many practical mathematical and physical problems. Recently, Intel released Xeon Phi, a many-core processor of Intel’s Many Integrated Core (MIC) architecture, comprises 60 cores and supports 512-bit SIMD operation. In this work, we aim at accelerating an iterative algorithm for large spare linear system, named PQMRCGSTAB, by using both Xeon Phi’s 8-way vector operation and dense threads. Then, we propose three optimizations to improve the performance: data prefetching to hide the data latency, vector register reusing, and SIMD-friendly reduction. Our experimental evaluation on Xeon Phi delivers a speedup of close to a factor 6 compared to the Intel Xeon E5-2670 octal-core CPU running the same problem.