High-Level Synthesis from C vs. a DSL-Based Approach
Cristiano Bacelar de Oliveira, João M. P. Cardoso, Eduardo Marques · 2014
Field-Programmable Gate Arrays (FPGAs) are able to provide hardware accelerators still maintaining the required programmability. However, the advantages of using FPGAs still depend on the expertise of developers and their knowledge of Hardware Description Languages (HDLs). Although High-level Synthesis (HLS) tools have been developed in order to minimize this problem, they commonly present solutions considered many times inefficient when compared to the ones achieved by a specialized hardware designer. Domain-specific languages (DSLs) can provide alternative solutions to program FPGAs. They can provide higher abstraction levels than HDLs and they may allow the programmer to tune implementations whenever HLS tools are unable to generate efficient designs. In this paper we compare a DSL, named LALP (Language for Aggressive Loop Pipelining), with two typical HLS approaches and show the experimental results achieved in each case. The results show that the use of LALP provides superior performance than the achieved by the HLS tools in most cases.