Design, testing and applications of four-valued pads
Antonio J. Acosta, M. Valencia, A. Barriga, M.J. Bellido, J.L. Huertas · International Journal of Electronics · 1993
A family of multiple-valued static pads built using standard 1 · 5 µm CMOS technology is presented. It consists of an input pad (one four-valued input and two binary outputs), an output pad (two binary inputs and one four-valued output) and an additional pad for test purposes. The most obvious advantage of these pads is the area gained (50%), as compared to their binary counterparts. Testability issues are included, as well as test circuitry to measure the performance of these pads. This family can be used in chips with very high pinout requirements, decreasing the complexity of the interconnections at a board level. An improved boundary scan scheme is presented, as an additional application of four-valued pads.