ON THE REDUCTION OF INTERCONNECT EFFECTS IN DEEP SUBMICRON IMPLEMENTATIONS OF DIGITAL MULTIPLICATION ARCHITECTURES
P. Mokrian, Majid Ahmadi, GRAHAM A. JULLIEN · Journal of Circuits Systems and Computers · 2006
The conventional trend in algorithm implementation has been the reliance on advancements in process technology in order to satisfy the ever-increasing demand for high-speed and low power processors, and computational systems. As current device technology approaches sub-100 nm minimum device size, not only does the device geometry decrease, but switching times and operating voltages also scale down. These gains come at the expense of increased layout complexity, and a greater susceptibility to parasitic effects in the interconnections. In this paper we briefly overview the challenges that digital arithmetic designers will have to face in the imminent future, and we provide suggestions on algorithmic measures which may be taken in order to overcome some of these challenges. To illustrate our point, we will present an analysis of a digital multiplication algorithm, which is predicted to outperform currently preferred architectures for future technologies. We then apply the algorithm to form a multiplier architecture that alleviates many of the problems associated with interconnect scaling; in addition, our new architecture allows for simple variable precision reconfiguration.